Summary
docker/rocm.Dockerfile pins AITER_COMMIT_DEFAULT=d9e5ef7ce08ee7045d583aed768cff41aa9210fe (ROCm/aiter, 2026-07-29) for all four arch stages. That pin predates ROCm/aiter db24351e — "[fmoe][gfx950] Flydsl mxmoe v2" (#4179), 2026-08-04, which introduces the flydsl_mxmoe_* / flydsl_moe2_layout_* FlyDSL MXFP4 fused-MoE kernel families.
Consequence on gfx950: SGLang cannot consume an AITER-tuned MXFP4 fused-MoE table (AITER_CONFIG_FMOE), and cannot produce one either, so the tuned-MoE kernel-selection path is unavailable on published ROCm images.
Repro
Load any AITER_CONFIG_FMOE table tuned with AITER ≥ db24351e (rows naming flydsl_mxmoe_* kernels) — the scheduler dies at model load on every TP rank:
ValueError: Invalid FlyDSL kernel name: flydsl_mxmoe_g1_a4w4_16x256x256_f16in_nt
raised from aiter/fused_moe.py after aiter.ops.flydsl.moe_kernels.get_flydsl_kernel_params() returns None.
Probing the registry inside the published images confirms the cause is the pin, not the table. Model GLM-5.2-MXFP4, TP4, gfx950 (MI350X); 4 distinct kernel names in the table:
| image |
published |
bundled AITER |
FlyDSL registry size |
table's kernels resolved |
--mxfp4-flydsl tuner mode |
lmsysorg/sglang:v0.5.16-rocm720-mi35x |
2026-07-24 |
9127c94a (06-25) |
3393 |
0 / 4 |
no |
lmsysorg/sglang:v0.5.17-rocm720-mi35x |
2026-08-08 |
d9e5ef7c (07-29) |
4257 |
0 / 4 |
no |
Both registries contain only the older flydsl_moe1_* / flydsl_moe2_* families (1057 of them afp4_wfp4 in v0.5.16) — zero entries matching mxmoe, a4w4, or layout.
Note v0.5.17's image was published four days after the floor commit while its AITER pin is six days before it, so the image tag date is not a reliable proxy here.
Retuning locally is not a workaround: the bundled csrc/ck_gemm_moe_2stages_codegen/gemm_moe_tune.py at this pin has no MXFP4-FlyDSL mode (--grouped-gemm is gfx1250-only), so --mxfp4-flydsl is rejected with unrecognized arguments.
Impact
On MI350X/gfx950 with GLM-5.2-MXFP4 (TP4), the tuned MXFP4 MoE table measured +7.5–12.9% end-to-end output throughput at concurrency 16–64 on an engine that can load it (kernel-level: +21.6% at M=32, +19.1% at M=16, +7.7% at M=1; 6 of 11 shapes improved past a 3% gate). That gain is currently unreachable from any published SGLang ROCm image.
Suggested fix
Bump AITER_COMMIT_DEFAULT to a commit ≥ db24351e (or current AITER main) — at minimum for the gfx950 / gfx950-rocm720 stages. This follows the existing routine-bump precedent (#28248, #28249, #27555, #27376).
Users can already work around it today via the documented build arg (thanks to #21949):
docker build -f docker/rocm.Dockerfile --build-arg GPU_ARCH=gfx950-rocm720 \
--build-arg AITER_COMMIT=<commit ≥ db24351e> .
Happy to submit the bump PR if a maintainer confirms which AITER commit you'd like to land on — I have a gfx950 (MI350X) node and can validate GLM-5.2-MXFP4 TP4 serving plus the tuned-table load before opening it.
Environment
- 8× MI350X (gfx950), ROCm 7.2, TP4
- Model: GLM-5.2-MXFP4
- Images as tabled above; probe via
aiter.ops.flydsl.moe_kernels.get_flydsl_kernel_params(name) is not None
Summary
docker/rocm.DockerfilepinsAITER_COMMIT_DEFAULT=d9e5ef7ce08ee7045d583aed768cff41aa9210fe(ROCm/aiter, 2026-07-29) for all four arch stages. That pin predates ROCm/aiterdb24351e— "[fmoe][gfx950] Flydsl mxmoe v2" (#4179), 2026-08-04, which introduces theflydsl_mxmoe_*/flydsl_moe2_layout_*FlyDSL MXFP4 fused-MoE kernel families.Consequence on gfx950: SGLang cannot consume an AITER-tuned MXFP4 fused-MoE table (
AITER_CONFIG_FMOE), and cannot produce one either, so the tuned-MoE kernel-selection path is unavailable on published ROCm images.Repro
Load any
AITER_CONFIG_FMOEtable tuned with AITER ≥db24351e(rows namingflydsl_mxmoe_*kernels) — the scheduler dies at model load on every TP rank:raised from
aiter/fused_moe.pyafteraiter.ops.flydsl.moe_kernels.get_flydsl_kernel_params()returnsNone.Probing the registry inside the published images confirms the cause is the pin, not the table. Model GLM-5.2-MXFP4, TP4, gfx950 (MI350X); 4 distinct kernel names in the table:
--mxfp4-flydsltuner modelmsysorg/sglang:v0.5.16-rocm720-mi35x9127c94a(06-25)lmsysorg/sglang:v0.5.17-rocm720-mi35xd9e5ef7c(07-29)Both registries contain only the older
flydsl_moe1_*/flydsl_moe2_*families (1057 of themafp4_wfp4in v0.5.16) — zero entries matchingmxmoe,a4w4, orlayout.Note v0.5.17's image was published four days after the floor commit while its AITER pin is six days before it, so the image tag date is not a reliable proxy here.
Retuning locally is not a workaround: the bundled
csrc/ck_gemm_moe_2stages_codegen/gemm_moe_tune.pyat this pin has no MXFP4-FlyDSL mode (--grouped-gemmis gfx1250-only), so--mxfp4-flydslis rejected withunrecognized arguments.Impact
On MI350X/gfx950 with GLM-5.2-MXFP4 (TP4), the tuned MXFP4 MoE table measured +7.5–12.9% end-to-end output throughput at concurrency 16–64 on an engine that can load it (kernel-level: +21.6% at M=32, +19.1% at M=16, +7.7% at M=1; 6 of 11 shapes improved past a 3% gate). That gain is currently unreachable from any published SGLang ROCm image.
Suggested fix
Bump
AITER_COMMIT_DEFAULTto a commit ≥db24351e(or current AITER main) — at minimum for thegfx950/gfx950-rocm720stages. This follows the existing routine-bump precedent (#28248, #28249, #27555, #27376).Users can already work around it today via the documented build arg (thanks to #21949):
Happy to submit the bump PR if a maintainer confirms which AITER commit you'd like to land on — I have a gfx950 (MI350X) node and can validate GLM-5.2-MXFP4 TP4 serving plus the tuned-table load before opening it.
Environment
aiter.ops.flydsl.moe_kernels.get_flydsl_kernel_params(name) is not None