SM120 NVFP4 KV cache support + MTP cudagraph fix + KV offload crash fix

[ch2lab]

Summary

This PR adds SM120 (RTX 5090, Blackwell consumer) NVFP4 KV cache support to vLLM, fixes MTP cudagraph routing for draft models, and fixes a crash in KV offloading when requests are aborted mid-transfer.

Changes

1. SM120 NVFP4 KV Cache Support (flashinfer.py, flashinfer.py utils)

SM120 does not support native TRTLLM-GEN cubins, so NVFP4 KV cache must route through the FlashInfer FA2 Tensor-Core native path. Changes include:

• supports_kv_cache_dtype: Declare NVFP4 support for SM120 FA2 path
• HND layout: Use 4-D (B, 2*N_kv, N, F) layout instead of 5-D for contiguous strides with reshape_and_cache_flash
• use_fa2_nvfp4_kv flag: Routes SM120 NVFP4 through FA2 native instead of trtllm-gen
• Backend selection: Correct backend chosen for SM120 NVFP4 prefill and decode
• kv_data_type=torch.uint8: NVFP4 data stored as uint8 pairs
• o_dtype=BF16: Output dtype for FA2 NVFP4 path
• Cudagraph prefill wrappers: Support cudagraph capture for prefill wrappers on SM120
• _uniform_decode_query_len: Return correct query length for uniform decode batches
• _prefill_wrappers_cudagraph: Properly handle prefill wrapper cudagraph capture
• _prefill_qo_indptr_gpu: GPU-side qo_indptr for prefill
• needs_fp8_out guards: Skip FP8 output checks for NVFP4 path

2. MTP Cudagraph Fix (llm_base_proposer.py, gpu_model_runner.py, dflash.py, extract_hidden_states.py)

Fixes MTP (Multi-Token Prediction) speculative decoding performance by ensuring correct cudagraph mode routing:

• initialize_cudagraph_keys: Use cudagraph_mode directly instead of forcing PIECEWISE for eagle draft
• propose() first pass: Detect uniform decode (max_query_len == 1) and pass uniform_decode hint to dispatcher, enabling FULL cudagraph matching
• Auto-regressive loop: Pass uniform_decode=True since all subsequent drafts are pure decode
• dummy_run(): New target_cudagraph_mode parameter to pass the target model's cudagraph mode
• gpu_model_runner.py: Allow FULL cudagraph for draft model; pass target_cudagraph_mode to drafter
• _determine_batch_execution_and_padding: New forced_cudagraph_mode and uniform_decode parameters for explicit cudagraph control
• API compatibility: dflash.py and extract_hidden_states.py accept new target_cudagraph_mode parameter

3. KV Offload Crash Fix (offloading/scheduler.py, offloading_connector.py)

Fixes a crash when a request is aborted while KV blocks are mid-transfer in the offloading connector:

• update_offload_keys(): New limit_by_block_ids parameter to scope key updates to specific blocks
• request_finished(): New block_ids parameter to properly clean up only the blocks belonging to the finished request
• offloading_connector.py: Passes block_ids to request_finished() in both single and group completion paths

4. JIT Warmup (gpu_worker.py)

• Added profile_run() before memory_profiling() to trigger FlashInfer JIT compilation early, preventing OOM during cudagraph capture when kernels compile on-demand.

Test Plan

• Verified on RTX 5090 (SM120) with Qwen3-Next / Gemma-4 models using NVFP4 KV cache
• Verified MTP speculative decoding achieves expected speedup with NVFP4 KV cache
• Verified KV offloading no longer crashes on aborted requests
• Verified BF16 and FP8 KV cache paths remain unaffected

[claude]

Claude Code Review

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[seanyourhighness]

Important integration note from long-context MTP validation

I tested the MTP/GDN stack on SM120 and found a separate missing spec-decode route in the FlashInfer XQA integration; I posted the full correction and red/green evidence in #49010.

The important point for this PR: its current SM12x attention changes intentionally select native FA2 rather than XQA (use_trtllm_decode_attention is disabled for the SM12x family). That is a valid baseline choice, but it means this PR's current end-to-end path is not the masked-XQA path I validated.

For MTP n=3, verification is q_len=4. The selected native decode route must either:

1. use uniform multi-token native decode with q_len_per_req (the direction in [Perf] SM120 PCIe serving stack: SP/async-TP enablement, FlashInfer spec-decode FULL cudagraphs, and PCIe-safe multi-GPU comms #47979, when the installed FlashInfer supports it), or
2. retain a deliberately tested prefill/PIECEWISE fallback.

Please do not treat MTP throughput alone as a correctness proof here: the failure was fluent, non-NaN, and only visible on long-context recall. The required gate is cold plus cached multi-request 32k+ recall under the exact selected backend.

Recommendation: keep the SM12x NVFP4 and drafter-routing work here, but share a backend-capability resolver with #47979 and the masked-XQA follow-up rather than hard-coding a model/SKU-specific MTP path. That resolver should decide native vs XQA vs TRTLLM-GEN, whether uniform spec decode is supported, whether a mask is required, and whether FULL capture is legal.

[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @ch2lab.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

[seanyourhighness]

Follow-up SM120 integration result: NVFP4 KV + MTP-3 at eight streams

Adding a larger consumer-Blackwell integration datapoint to my earlier comments. This is a combined local stack, not a checkout of the current PR head, so treat it as validation of the target SM120 NVFP4-KV/XQA route rather than isolated causal proof for every hunk.

Environment: RTX 5090 / SM120, CUDA 13, Qwen3.8-27B NVFP4, NVFP4 KV, MTP-3, async scheduling, FULL_AND_PIECEWISE graphs.

• max_num_seqs=8, graph capture sizes 4,8,12,16,20,24,28,32
• 8 GiB pinned KV pool: 373,797 tokens
• All graphs through 32 captured successfully; 2.3 GiB VRAM remained free
• Raw c8 decode: 744.1 tok/s aggregate, per-stream median 108.3, minimum 99.8
• Forced eight-active 6K-token replay: 857.4 tok/s aggregate, median 122.2, minimum 107.2; zero streams below 75
• Seven decoders plus 120K arriving prefill: 35.3 s prefill wall, 0.95 s maximum decode gap
• Real parent + seven-child soak: zero 500/FSM/grammar/OOM failures; KV peaked at 81%

No eager fallback, preemption, token-0 collapse, or mixed-prefill/decode failure was observed. Raw artifacts and the exact launcher are available if useful for review.

Disclosure: AI-assisted analysis and comment posting; the runs and measurements were produced and verified by me on the hardware described.