[Bugfix][Platform] sm12x: add FLASHMLA_SPARSE (Triton sparse-MLA) to the MLA-sparse backend candidate list — flashinfer sparse_mla_sm120 livelocks on GB10

[marksunner]

Summary

FlashInfer's sparse-MLA attention kernels (sparse_mla_sm120) livelock GB10 (sm_121) GPUs under cold-prefill load, wedging entire TP clusters with no host-side recovery path. This PR makes the Triton sparse-MLA route (FLASHMLA_SPARSE) selectable on sm12x, so affected deployments can bypass the livelocking kernels with a single backend flag. The root-cause evidence (cuda-gdb on a live wedge), validation receipts (560+ clean sessions), and full write-up live in the evidence repo and RFC #48720.

On capability-12 devices the MLA-sparse candidate list currently resolves to [TRITON_MLA, FLASHINFER_MLA_SPARSE_SM120] (vllm/platforms/cuda.py:130 in 0.23.1rc1.dev893+gd3a66aa7e); for sparse-MLA models (e.g. GLM-5.2 / DeepSeek-lineage MTP configs) the flashinfer sm120 path is the only viable pick — boot log receipt: Using FLASHINFER_MLA_SPARSE_SM120 … out of potential backends: ['FLASHINFER_MLA_SPARSE_SM120'] — so affected hardware has no escape hatch.

Enum-to-implementation map, for reviewers cold to the sparse-MLA backend zoo: FLASHINFER_MLA_SPARSE_SM120 is the flashinfer sparse_mla_sm120 CUDA kernel family (the livelocking one). FLASHMLA_SPARSE upstream binds the native FlashMLA CUDA extension (vllm._flashmla_C), which does not build/exist on sm12x; on our deployment the sm12x Triton drop-ins rebind its two sparse ops (flash_mla_sparse_fwd, flash_mla_with_kvcache) to portable Triton implementations — the Triton kernels come verbatim from the deepseek_v4 path of jasl's vLLM fork (credit @jasl) — so selecting FLASHMLA_SPARSE routes to Triton there. TRITON_MLA is the dense-MLA Triton backend, not a sparse-MLA implementation, so it is not viable for this model class — which is why the flashinfer path is today's sole effective candidate.

Ask: make the Triton sparse-MLA implementation (FLASHMLA_SPARSE backend enum) a member of the sm12x candidate list (ranked above the flashinfer sm120 path until the kernel race is fixed), or at minimum honor --attention-backend FLASHMLA_SPARSE for the main model on sm12x. The Triton kernels have no inter-block mbarrier/TMA dependencies and are structurally immune to this livelock class.

Evidence (cuda-gdb on a live wedge, 2026-07-17)

• Spinning device kernel: sparse_mla_prefill_kernel<(ModelType)2,(ComputeMode)0,16,2048,64> (flashinfer sparse_mla_sm120 family, csrc/sparse_mla_sm120_prefill.cu), param type PrefillColdParams.
• Grid (120,1,1) with one resident block, warps 8–11 all lanes active, non-divergent, spinning at SYNCS.PHASECHK.TRANS64.TRYWAIT P0[UR8+0x14980] → @P0 BRA loop — an mbarrier phase TRYWAIT spin: TMA/expect-tx arrive-wait race.
• Device signature during wedge: 96 % GPU util at ~18 W, 0 % memory utilization, clocks P0; host threads piled in cuLaunchKernel behind the jammed queue (making innocent kernels — marlin GEMMs, Triton ops — look guilty in host stacks; they were bystanders).
• Exonerations by receipt: RoCE fabric hw_counters all zero during a live wedge; driver/kernel identical pre/post-reboot (NVRM 580.159.03, kernel 6.17.0-1026); memory headroom falsified as cause (froze with 4.4–7.1 GB free); chunk size (8192→2048), max_num_seqs (6→3), served ceiling (200K→120K) all falsified as remedies, n≥2 each.
• Blast radius: 8 distinct freeze incidents across 2 days, on fresh boots, all previously misattributed (marlin/UMA, memory exhaustion, single-node hardware). One incident wedged on the FP8 decode-kernel route as well (MIN_HEADS reroute) — the race lives in shared sm120-family machinery, not one kernel.
• Full dossier (attach or link): nvidia-addendum/sparse-mla-sm120-mbarrier-livelock-20260717.md; NVIDIA bug filed separately.

Fix validated (route swap = the only variable)

Deployment fact, stated precisely: the sm12x Triton drop-ins were installed and exercised by the drafter throughout the campaign — a constant, present in every round on both sides of the swap — and the flipped variable was the main model's backend selection only. Routing the main model to the Triton sparse-MLA stack (--attention-backend FLASHMLA_SPARSE) with everything else pinned:

• The failing regime (cold staged prefill) went from 8/8 wedges to clean on the first attempt: 64-stage climb through 119,856 tok, every stage OK.
• 90 consecutive context-ceiling sessions (seq = ceiling−3..ceiling, temp 1.2) across all three drafter-gate modes, zero wedges; extended to 500 consecutive ceiling sessions overnight, zero wedges.
• Determinism spot-check (not a general correctness proof): the smoke completion — fixed prompt "The capital of France is", temperature 0, max_tokens 16 — returned byte-identical text across every healthy boot pre- and post-route-swap; the comparison scope is that single 16-token greedy completion.
• The drafter had run the same Triton route at every decode step of the campaign — long-baked-in evidence of stability.

Proposed change (shape)

1. vllm/platforms/cuda.py (capability-12 MLA-sparse selection): add FLASHMLA_SPARSE's Triton implementation to the candidate list for sm12x, preferred over FLASHINFER_MLA_SPARSE_SM120 until the mbarrier race is resolved upstream; keep flashinfer selectable explicitly.
2. Ensure --attention-backend FLASHMLA_SPARSE is honored for the main model on sm12x (today it is effectively reachable only via spec-config attention_backend for the drafter).
3. Log the fallback reason when flashinfer sm120 is skipped/deprioritized on sm12x so users can correlate with this issue.

Caveats / honest scope

• The livelock is probabilistic per cold-prefill tile count: quiet short-context or warm-cache serving will NOT reproduce it; staged cold prefill at ≥2.4K-token deltas reproduced it within seconds on our fleet.
• Perf: Triton route throughput vs the flashinfer baseline is measured in our write-up (the cure's cost is a number, stated there); selector preference may want a perf note.
• Generalization, softened to what we actually know: the race is in kernel-internal barrier logic and plausibly family-wide across sm12x; our validation covers only one model family (GLM-5.2 int4-int8mix, TP=4, MTP spec=4) on GB10 4× DGX Spark; other sm12x targets are untested.

Validation context and base

All validation above was performed on our production deployment, which is built from the jasl fork lineage (vLLM 0.23.1rc1.dev893+gd3a66aa7e). This branch is the port of that change onto upstream main at 3775d5f.

The port is compile-checked but has not been re-executed against the upstream base; happy to rebase onto current main on maintainer request.

AI-assistance disclosure (per AGENTS.md §1 Accountability)

AI assistance was used throughout this contribution. The investigation, evidence collection (cuda-gdb captures, RAS monitoring, soak testing), root-cause analysis, and drafting of this PR involved AI agents (Claude, operating as orchestrator and technical writer) under continuous human direction and review by @marksunner. All claims are backed by the linked evidence pack; every receipt cited in this PR description is a real artifact from the investigation.

Not duplicating an existing PR: No open PR addresses the sm12x sparse-MLA backend selection gap or the flashinfer sparse_mla_sm120 livelock. The closest related issues are #48720 (this RFC, filed by us) and #41725 (sampler event-sync hang — a separate bug class on the same platform).

Testing: Validation was performed on a 4× DGX Spark production deployment (GLM-5.2 int4-int8mix, TP=4, MTP spec=4). The branch is ported onto upstream main at 3775d5f and compile-checked; full re-execution results are from the jasl fork lineage deployment as disclosed in "Validation context and base" above. 560+ clean ceiling sessions, 500 consecutive under enforce, a 15-hour unattended overnight, and a cold staged climb to 200K tokens — all zero wedges. No model evaluation regression observed (decode throughput ≥25 tok/s, at or above the flashinfer baseline).

Refs

• RFC vllm-project/vllm [RFC] TP-wide step-consensus guard with NCCL RAS integration — field-validated, two live deadlock captures #48720 (this campaign's RFC; §4/§5 mechanism material, results update posted alongside this PR).
• Issue Recurring CUDA kernel hang on 2x DGX Spark (GB10, sm_12.1) with MiniMax-M2.7-NVFP4, TP=2 across 2 nodes #41725 (sm_12x sampler event-sync hang — separate disease, same platform; comment cross-posted).
• NVIDIA dossier: sparse-mla-sm120 mbarrier livelock (filed separately; kernel fix is theirs, this PR is the vLLM-side escape hatch).

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[claude]

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[marksunner]

Converting this to draft: upstream has moved roughly five hundred commits since our base, including significant refactors to deepseek_v2.py and flashmla_sparse.py, the exact areas this PR touches. Rather than force a risky rebase of a twelve-file change from outside the in-flight sparse-MLA work, we are parking this as a reference implementation. The validated changes against 3775d5f remain on the branch, and the full evidence, the cuda-gdb capture of the livelock and the 560-plus-session validation of the Triton route, is in the RFC 48720 update and the linked evidence repo. If maintainers closer to the current refactor prefer to integrate the escape hatch their own way, that outcome is the goal, happy to help however is useful. The companion PR #49027 is small and remains ready for review.