[Bugfix][CPU][RISC-V] Return zero below exp clamp bound

[HakureiPOI]

Preserve a mask from the unclamped input and merge positive zero into lanes below ln(FLT_MIN), matching the established x86 behavior for negative infinity and underflowing inputs.

Assisted-by: OpenAI Codex codex@openai.com

Purpose

Fix the RISC-V RVV FP32 fast-exp implementation returning FLT_MIN for inputs that should underflow to zero.

FP32Vec8::exp() and FP32Vec16::exp() clamp their inputs to:

exp_lo = ln(FLT_MIN)

before evaluating the polynomial approximation. Consequently, -inf and finite values strictly below exp_lo are evaluated as exp(exp_lo) and return FLT_MIN (0x00800000) instead of positive zero.

This behavior can be reached naturally by CPU attention. apply_mask() writes masked logits as -inf, which are then passed directly to the RVV fast-exp implementation. Although the resulting normalized weight is normally extremely small, a masked lane is no longer strictly excluded from the weighted sum.

This change records a strict input < exp_lo mask before clamping and merges +0.0f into those lanes after the existing polynomial calculation. The fix is applied to both FP32Vec8 and FP32Vec16.

The strict comparison preserves the existing boundary behavior:

• Inputs strictly below exp_lo, including -inf, return +0.0f.
• An input exactly equal to exp_lo still returns FLT_MIN.
• Ordinary finite inputs and the upper-bound behavior are unchanged.
• The existing NaN behavior is intentionally left unchanged.

No open PR was found that addresses the same underflow and special-value semantics. In particular:

• RISC-V ILP Optimization: Add instruction-level parallelism for transcendental functions #42900 adds instruction-level parallelism for transcendental functions and is a performance change.
• [Bugfix][CPU][RISC-V] Use explicit rounding mode for vfcvt float-to-int conversions #47983 changes the rounding mode used by float-to-integer conversions.

Neither changes the low-bound behavior addressed by this PR.

AI assistance was used during audit analysis, implementation, hardware validation, and preparation of this PR description. The submitter reviewed every changed line and is responsible for the change and validation results.

Test Plan

Run a before/after RVV intrinsic PoC on real RISC-V hardware using the same clamp, polynomial, exponent-scaling, LMUL, and mask operations as the production FP32Vec8::exp() and FP32Vec16::exp() implementations.

Test the following compiler and target combinations:

Compiler	Target
GCC 13.2	rv64gcv_zvfh_zvl128b
GCC 13.2	rv64gcv_zvfh_zvl256b
GCC 14.2	rv64gcv_zvfh_zvl128b
GCC 14.2	rv64gcv_zvfh_zvl256b

Representative compilation commands:

g++ -O2 -std=c++17 \
    -march=rv64gcv_zvfh_zvl128b \
    rv003_intrinsic_probe.cpp

g++ -O2 -std=c++17 \
    -march=rv64gcv_zvfh_zvl256b \
    rv003_intrinsic_probe.cpp

The inputs cover:

• -inf;
• nextafter(exp_lo, -inf);
• exactly exp_lo;
• ordinary negative, zero, and positive finite values;
• +inf; and
• NaN as an unchanged-behavior control.

Also run an attention-style causal-mask PoC with one visible zero logit and fifteen masked -inf logits. Set the value belonging to a masked position to 2**126 so that the incorrect FLT_MIN weight becomes observable in the output.

Run the source checks:

pre-commit run clang-format \
    --files csrc/cpu/cpu_types_riscv_impl.hpp

pre-commit run typos \
    --files csrc/cpu/cpu_types_riscv_impl.hpp

git diff --check

Test Result

The hardware validation was run on:

Host: bianbu / k1
CPU: Spacemit X60
Architecture: riscv64
Runtime VLEN: 256 bits
Compilers: GCC 13.2 and GCC 14.2

All four compiler/target combinations produced the expected before/after behavior for both the FP32Vec8-equivalent and FP32Vec16-equivalent paths.

Input or scenario	Before	After
-inf	FLT_MIN (0x00800000)	+0.0f (0x00000000)
nextafter(exp_lo, -inf)	FLT_MIN	+0.0f
exactly exp_lo	FLT_MIN	FLT_MIN
ordinary finite values	Existing result	Unchanged
+inf	+inf	+inf
NaN	Existing result	Unchanged

The attention-style PoC produced:

# Before
causal_q0 visible_exp=0x1p+0 masked_exp=0x1p-126
masked_weight=0x1p-126 amplified_output=0x1p+0 sum=0x1p+0

# After
causal_q0 visible_exp=0x1p+0 masked_exp=0x0p+0
masked_weight=0x0p+0 amplified_output=0x0p+0 sum=0x1p+0

Without amplification, an attention row containing one masked -inf logit and fifteen zero logits produced a masked normalized weight of approximately 7.84e-40. This confirms the special-value correctness issue, but does not establish a significant output difference for ordinary model requests.

Local validation:

clang-format pre-commit hook: passed
typos pre-commit hook: passed
git diff --check: passed

A full single-file pre-commit invocation also reached the repository-wide update-dockerfile-graph hook, which could not run in the native Windows environment because /bin/bash was unavailable. The source-specific applicable hooks passed.

No new pytest coverage is included in this PR. The current dynamic validation uses a production-equivalent RVV intrinsic PoC on real hardware. A complete patched vLLM CPU extension build, full cpu_attn operator test, and model-level evaluation have not yet been completed.

Therefore, this PR currently establishes:

• reproduction of the incorrect RVV exp semantics on real hardware;
• correct boundary behavior after the fix;
• compiler compatibility with GCC 13.2 and GCC 14.2;
• correct ZVL128 and ZVL256 LMUL/mask behavior; and
• removal of the observable masked-value contribution in the targeted PoC.

It does not claim a measurable output or accuracy impact for ordinary model workloads.

---

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